Successful cyber attacks often leverage the fact that an instruction set architecture of a target system is well known. Given knowledge of the instruction set architecture, attackers can prepare malicious software, knowing with high confidence that it will run once introduced into the target system via code-injection attacks or other attack vectors.
Instruction stream randomization (ISR) seeks to thwart these attacks by creating unique, dynamic system architectures, thus denying attackers the asymmetric advantage of a well-known target architecture by forcing them to expend considerable resources for each system they wish to compromise. However, previous ISR research has been hampered by the need for hardware emulators to implement the necessary changes to the CPU.